The present disclosure relates to a storage device that includes a memory cell having a storage element and a switching element, and particularly to a storage device having a drive source for rerecording by verification control and an information rerecording method.
In information equipments such as a computer, a high density DRAM (Dynamic Random Access Memory) capable of high speed operation is widely used. However, in the DRAM, there is a problem that the manufacturing cost is high, since the manufacturing process is more complicated than that of a general logical circuit, a general signal processing circuit or the like used for electronic devices. Further, since the DRAM is a volatile memory in which information is not retained if the power is turned off, it is necessary to perform refresh operation frequently.
Thus, as a nonvolatile memory in which information is retained even if the power is turned off, for example, an FeRAM (Ferroelectric Random Access Memory), an MRAM (Magnetoresistive Random Access Memory) and the like have been proposed. In these memories, even if power is not supplied, written information is able to be retained for a long time. In addition, in these memories, it is not necessary to perform refresh operation, and thus power consumption is able to be decreased by just that much. However, there is a problem that miniaturization is not easy in the FeRAM, while there is a problem that a writing current is large in the MRAM (for example, Nonpatent Document 1).
Therefore, as a memory suitable for speeding up the data writing speed, for example, a new type storage device as illustrated in FIG. 9 and FIG. 10 has been proposed.
FIG. 9 illustrates a memory cell 100 of the storage device. The memory cell 100 includes a variable resistive element 110 whose cross sectional structure is illustrated in FIG. 10 and an MOS transistor 120 (switching element). The variable resistive element 110 is formed by layering an electrode 111, an ion source layer 112, a high resistive layer 113, and an electrode 114. The electrode 111 is electrically connected to a bit line BLR, and the electrode 114 is electrically connected to one terminal of the MOS transistor 120, respectively. The other terminal of the MOS transistor 120 is electrically connected to a bit line BLT, and a gate of the MOS transistor 120 is electrically connected to a word line WL, respectively.
In the storage device, when a voltage is applied to the electrode 114 and the electrode 111 so that a current is flown from the ion source layer 112 to the high resistive layer 113, state of the high resistive layer 113 is changed to low resistance, and data is written. By contraries, when a voltage is applied to the electrode 114 and the electrode 111 so that a current is flown from the high resistive layer 113 to the ion source layer 112, state of the high resistive layer 113 is changed to high resistance, and data is erased.
Compared to the existing nonvolatile memory or the like, the storage device has features that no element size dependence exists since the memory cell is able to be structured by a simple structure, and the storage device is good at scaling since a large signal is able to be obtained. Further, the storage device has advantages that data writing speed due to resistance change is able to be speeded up to, for example, about 5 nanoseconds, and the storage device is able to be operated by a low voltage (for example, about 1 V) and a low current (for example, about 20 μA).
Nonpatent document 1: Nikkei Electronics, issue date: Jul. 16, 2007, p. 98
However, in the foregoing storage device, when writing is performed by the existing method, the following problems occur. That is, in order to perform optimal writing into such a kind of storage device, it is necessary to control a voltage and a current applied to the variable resistive element 110 so that the voltage and the current fall within a given range. FIG. 11 illustrates an equivalent circuit at the time of writing thereof. Voltage control is performed by adjusting a voltage (VBLR) of the bit line BLR mainly by a VBLR adjustment circuit 121, and current control is performed by adjusting a voltage (VWL) of the word line WL mainly by a VWL adjustment circuit 122, respectively. As described above, for performing optimal writing by the existing method, the adjustment circuits for controlling two voltages are necessitated. It results in a factor to cause increase of peripheral circuit size.
Further, in some cases, controlling the foregoing VBL and the foregoing VWL is performed as default setting before shipment for every cell or for every block unit as a group composed of several cells. In some cases, adjustment is performed for every cell and for every writing operation. Examples of general techniques of the latter case include a method in which verification reading and rewriting are combined (hereinafter collectively and simply referred to as verification). That is, in such a method, verification reading is performed after writing operation. In the case of low resistance, it is determined that writing has succeeded and writing operation is finished. Meanwhile, in the case of high resistance, it is determined that writing has failed and rewriting is performed. Such a cycle is repeated until a certain upper limit number of cycles is completed.
If writing fails, it is prospective that optimal conditions of a voltage and a current have been changed to higher level. Thus, in the case where rewriting is performed, both voltages VBL and VWL are increased than in the precedent writing to improve writing success rate. To realize such complicated control, increase of the peripheral circuit is inevitable. However, as described above, in the existing technique, it is necessary to control two voltages, leading to further increase of peripheral circuit size.
In view of the foregoing problems, it is desirable to provide a storage device and an information rerecording method that decrease the number of voltages necessitating control and are able to decrease peripheral circuit size.